Maximum power estimation for CMOS circuits under arbitrary delay model

Estimation of maximum power dissipation is important in designing highly reliable VLSI systems. However, maximum power estimation for CMOS circuits is essentially a combinatorial optimization problem, which has exponential complexity in the worst case. For large-scaled circuits, it is CPU time intensive to exhaustively search for the optimal input patterns to induce maximum power. The feasible way is to generate tight upper and lower bounds of the maximum power, and make the gap between the bounds as narrow as possible. In this paper, we estimate maximum power consumption of CMOS circuits considering glitching activity and process variations. Given a circuit and the gate library, a Monte-Carlo based technique is developed to determine the maximum power from a statistical point of view. In our experiments with ISCAS-85 benchmarks, the ratio of the maximum power with glitching activity over the maximum power under zero-delay model ranges from 1.22 to 2.67. In the average power consumption case, our experiments show that glitching activity accounts for 13% to 48% of the total power