Integrated scheduling and register assignment for VLIW-DSP architectures

This paper describes code generation techniques for VLIW-DSP architectures. We focus on architectures with heterogeneous functional units and heterogeneous register sets. When generating code, scheduling and register allocation/assignment are typically done in separate steps. This is due to the fact that these tasks are complex combinatorial optimization problems particularly in case of irregular data-paths. However, these phases are strongly interdependent and therefore traditional approaches are often suboptimal. This paper proposes a new technique to integrate scheduling and register assignment. Our approach ensures that only schedules are produced for which a register assignment is guaranteed to exist. This is achieved by mapping the register set of the architecture onto a set of virtual resources. The concept of virtual resources provides a powerful methodology to easily check whether a register assignment for a specific schedule exists without the necessity to generate one. This allows to apply any schedule generation or optimization strategy and register assignment to be done only for the optimized final schedule for which a solution is known to exist