VLSI Reed Solomon decoder architecture for networked multimedia applications

Author

Martina, Maurizio ; Masera, Guido ; Piccinini, Gianluca ; Vacca, Fabrizio ; Zamboni, Maurizio

Author_Institution

Dipt. di Elettronica, Politecnico di Torino, Italy

fYear

2001

fDate

6/23/1905 12:00:00 AM

Firstpage

347

Lastpage

351

Abstract

In this paper a novel VLSI Reed Solomon decoder architecture is presented. During the design flow, particular care has been posed to the methodology used in order to grant a great degree of reusability. The obtained decoder core is very suitable for complex System On Chip (SoC) based applications, common in networking environments. In fact, thanks to the high reliability allowed by advanced channel coding techniques, the architecture developed has interesting figures of simplicity and speed. Logic synthesis on a FPGA device has shown an operating frequency up to 86 MHz with a core area of just 447 cells

Keywords

Reed-Solomon codes; VLSI; decoding; digital signal processing chips; field programmable gate arrays; high-speed integrated circuits; multimedia communication; 86 MHz; FPGA device; RS decoder core; VLSI Reed-Solomon decoder architecture; channel coding techniques; complex SoC based applications; networked multimedia applications; system on chip based applications; Channel coding; Decoding; Error correction; Error correction codes; Field programmable gate arrays; Logic; Network synthesis; Reed-Solomon codes; System-on-a-chip; Very large scale integration;

fLanguage

English

Publisher

ieee

Conference_Titel

ASIC/SOC Conference, 2001. Proceedings. 14th Annual IEEE International

Conference_Location

Arlington, VA

Print_ISBN

0-7803-6741-3

Type

conf

DOI

10.1109/ASIC.2001.954725

Filename

954725