CID/DRAM mixed-signal parallel distributed array processor

Author

Genov, Roman ; Cauwenberghs, Gert

Author_Institution

Dept. of Electr. & Comput. Eng., Johns Hopkins Univ., Baltimore, MD, USA

fYear

2001

fDate

6/23/1905 12:00:00 AM

Firstpage

391

Lastpage

395

Abstract

Presents a mixed-signal distributed VLSI architecture for massively parallel array processing, with fine-grain embedded memory. The three-transistor processing element in the array combines a charge injection device (CID) binary multiplier and analog accumulator with embedded dynamic random-access memory (DRAM). A prototype 512×128 vector-matrix multiplier on a single 3 mm×3 mm chip fabricated in standard CMOS 0.5 μm technology achieves 8-bit effective resolution and dissipates 0.5 pJ per multiply-accumulate

Keywords

VLSI; mixed analogue-digital integrated circuits; multiplying circuits; parallel architectures; random-access storage; 0.5 micron; 0.5 pJ; 8 bit; CID/DRAM architecture; VLSI architecture; analog accumulator; binary multiplier; charge injection device; effective resolution; embedded dynamic random-access memory; fine-grain embedded memory; mixed-signal parallel distributed array processor; multiply-accumulate operation; three-transistor processing element; vector-matrix multiplier; Array signal processing; Bandwidth; CMOS technology; Computer vision; Concurrent computing; Pattern recognition; Random access memory; Silicon; Throughput; Very large scale integration;

fLanguage

English

Publisher

ieee

Conference_Titel

ASIC/SOC Conference, 2001. Proceedings. 14th Annual IEEE International

Conference_Location

Arlington, VA

Print_ISBN

0-7803-6741-3

Type

conf

DOI

10.1109/ASIC.2001.954733

Filename

954733