A voltage-variable time delay element for clock waveforms

Voltage variable time delay circuits are a fundamental component of delay-locked loops (DLLs) in which an incoming periodic waveform is locked to a very stable reference clock signal. In this paper, a concept for a time delay circuit is experimentally demonstrated which provides a continuous delay of up to 40% of the period of the clock waveform. To achieve greater time delays, several units can be cascaded together. The circuit works by first detecting the clock transitions using an exclusive OR (XOR) gate. The transition detector generates pulses which are elongated in time by means of a monostable multivibrator. The output of the multivibrator is used to trigger a flip-flop (FF) and the delayed clock waveform is taken at the output of the FF.