Topologically advised terminal assignment of packages in multilayered circuitry

We found a situation where we can reduce costs by 50% due to adjusting terminal assignment. As the situation can be found in several technologies, we abstractly look at a "chip" on a "board". We generalize the "pinout of the package" to a system of eight rings of terminal assignment permutations (rotap). By means of the rotaps, it is shown that a randomly done terminal assignment can complicate both the outer layout of the board and the inner layout of the chip. We find topological disentangling having proper models to optimize the terminal assignment. By using cross-edge models, we can gain topological advice while minimizing transformations during modeling work. As a very little, but demonstrative, example, we work out an ASIC, concurrently designed with its dedicated PCB and having terminal assignment optimized. In addition we saved a layer of conductors on the PCB.