Improved ZDN-arithmetic for fast modulo multiplication

Sedlak (1987) proposed a modulo multiplication algorithm which is suitable for smart card implementation due to its low latency time. It is based on ZDN (Zwei-Drittel-N) arithmetic using an interleaved serial multiplication and reduction to calculate the product P=AB mod M. It can be shown that the maximum average reduction rate is theoretically limited to 3 bit/operation. In this paper we propose a modified left-to-right signed digit re-coding algorithm to receive an average shift of 4.5 bit/operation. Based on the presented ideas we also propose a modified reduction algorithm giving an average reduction rate of 4.5 bit/operation too. The speed up of our algorithms compared with the original algorithm is therefore 50%