DocumentCode
1602599
Title
Design alternatives for parallel saturating multioperand adders
Author
Balzola, Pablo I. ; Schulte, Michael J. ; Ruan, Jie ; Glossner, John ; Hokenek, Erdem
Author_Institution
Dept. EECS, Lehigh Univ., Bethlehem, PA, USA
fYear
2001
fDate
6/23/1905 12:00:00 AM
Firstpage
172
Lastpage
177
Abstract
Parallel saturating multioperand adders significantly improve the performance of global system for mobile (GSM) speech coders by giving compilers and assembly language programmers the ability to parallelize loops containing saturating dot products, while maintaining GSM compliant results. This paper presents four designs for parallel saturating multioperand adders. These designs have at most one carry-propagate adder on their critical delay path, yet produce the same results that would be obtained if the additions were performed serially with saturation after each addition. The four parallel designs offer tradeoffs in terms of area, worst case delay, and dot product latency. Compared to a 5-input serial design, the 5-input parallel designs have delays up to 3.51 times shorter
Keywords
cellular radio; digital arithmetic; feedback; parallel processing; telecommunication computing; vocoders; GSM speech coders; carry-save feedback; critical delay path; dot products; global system for mobile; parallel saturating multioperand adders; Arithmetic; Assembly; Concurrent computing; Delay estimation; Digital signal processing; Feedback; GSM; Pipelines; Program processors; Speech;
fLanguage
English
Publisher
ieee
Conference_Titel
Computer Design, 2001. ICCD 2001. Proceedings. 2001 International Conference on
Conference_Location
Austin, TX
ISSN
1063-6404
Print_ISBN
0-7695-1200-3
Type
conf
DOI
10.1109/ICCD.2001.955021
Filename
955021
Link To Document