DocumentCode
1604412
Title
Comparative analysis between the Stratix II (Altera) and Virtex 4 (Xilinx) for implementing a LVDS bus receiver
Author
Lujan, C.A. ; Mora, F.J. ; Martínez, J.D.
Author_Institution
Inst. Tecnologico de Merida, Merida
fYear
2007
Firstpage
373
Lastpage
376
Abstract
Technological advances mean that increasingly faster speeds are required for data transmission between devices, and also better tools and resources are required for connecting devices. When various solutions are available for solving data transmission problems, it is necessary to compare solutions to decide which is best for a given system. This paper compares two families of FPGAs both suitable for implementing an LVDS receiver de-serializer. The paper also describes the various tools that are available with each device for improving performance and increasing data transmission rates.
Keywords
data communication; field programmable gate arrays; receivers; system buses; telecommunication signalling; Altera; FPGA; LVDS bus receiver; LVDS receiver deserializer; Stratix II; Virtex 4; Xilinx; data transmission; low voltage differential signaling; Clocks; Data communication; Data engineering; Electromagnetic interference; Field programmable gate arrays; Frequency conversion; Logic devices; Multiplexing; Noise reduction; Table lookup; DCM; LVDS;
fLanguage
English
Publisher
ieee
Conference_Titel
Electrical and Electronics Engineering, 2007. ICEEE 2007. 4th International Conference on
Conference_Location
Mexico City
Print_ISBN
978-1-4244-1166-5
Electronic_ISBN
978-1-4244-1166-5
Type
conf
DOI
10.1109/ICEEE.2007.4345043
Filename
4345043
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