FinFET SRAM design challenges

The utilization of FinFET devices in the SRAM cell provides many benefits over planar bulk devices due to the fully-depleted behavior with improved subthreshold slope, short-channel effects, drive current, and mismatch. However, the quantized nature of the fins results in several new challenges as compared to planar devices. For the layout of the SRAM cell with FinFETs, the cell width needs to match up with the periphery fin pitch to provide a smooth transition from the cell array to the periphery. For the highest-density SRAM cell comprised of single fins for each device, the minimum Vdd (Vmin) of the write operation becomes substantially worse than the read operation, thus requiring the use of write assist techniques for low Vdd operation. This paper highlights tradeoffs in cell size and Vmin for different FinFET cell configurations and the simulated Vmin improvements with several different assist approaches.