• DocumentCode
    1605137
  • Title

    A class of systematic t/B-error correcting codes for semiconductor memory systems

  • Author

    Umanesan, Ganesan ; Fujiwara, Eiji

  • Author_Institution
    Graduate Sch. of Inf. Sci. & Eng., Tokyo Inst. of Technol., Japan
  • fYear
    2001
  • fDate
    6/23/1905 12:00:00 AM
  • Firstpage
    85
  • Lastpage
    86
  • Abstract
    This paper proposes a class of systematic codes called single t/B-error correcting - single b-bit byte error correcting - single b-bit block error detecting (StB/EC-SbEC-SBED) codes for high speed semiconductor memory systems. The proposed codes correct multiple random t-bit errors occurring within a chip and b-bit byte errors caused by sub-array data faults while simultaneously indicating B-bit block errors caused by complete chip failures
  • Keywords
    DRAM chips; error correction codes; error detection codes; DRAM chips; block error detecting codes; byte errors; chip failure; error correcting codes; information bit length; multiple random errors; semiconductor memory systems; sub-array data faults; systematic codes; Circuit faults; Computer errors; Control systems; Electromagnetic scattering; Encoding; Error correction; Error correction codes; Information science; Satellite broadcasting; Semiconductor memory;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Information Theory Workshop, 2001. Proceedings. 2001 IEEE
  • Conference_Location
    Cairns, Qld.
  • Print_ISBN
    0-7803-7119-4
  • Type

    conf

  • DOI
    10.1109/ITW.2001.955144
  • Filename
    955144
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=1605137