Delay Asymmetry Correction Model for Master-Slave Synchronization Protocols

This paper proposes a Delay Asymmetry Correction (DAC) Model to enhance clock synchronization protocols based on a Master-Slave arrangement such as the IEEE 1588 PTP protocol. The purpose of this work is to mitigate the effects of unpredictable packet delay variations (PDV), which may aggravate asymmetric link delays on timing packets, in order to improve the synchronization accuracy of the slave clock with respect to the master clock. The key idea in our work is to filter clock updates derived from the master-slave message exchange, using only good samples for slave clock updates. The proposed solution is implemented in Network Simulator 2 (NS-2.34). NS-2 test cases are implemented according to the ITU-T G.8261 document covering various network loads and network conditions. Our simulation results indicate that the proposed solution improves the slave accuracy significantly, achieving almost perfect synchronization accuracy in the presence of a wide range of network traffic loads, network congestions, and temporary network outage. Furthermore, when there is a routing path change due to the failure in the network, the solution also maintains high slave clock accuracy with respect to the master clock.