Design and implementation of enhanced crossbar CIOQ switch architecture

Author

Awan, A. ; Venkatesan, R.

Author_Institution

Fac. of Eng. & Appl. Sci., Memorial Univ. of Newfoundland, St. John´´s, Nfld., Canada

Volume

2

fYear

2004

Firstpage

1045

Abstract

Currently, combined input output queued (CIOQ) switches are being considered for high performance switch architectures. This is due to their ability to achieve high throughput and emulate output queued switch performance with a small speedup factor of 4 or 5. The paper presents the design and VLSI implementation of a 16×16 cell based CIOQ switch with enhanced crossbars to provide a speedup of 4 while operating the switch fabric at the line rate and memories at half the line rate. We describe the implementation of this architecture in VLSI using 0.18 micron CMOS standard-cell technology. We report on the design complexity and discuss implementation results. This architecture can handle a line rate of 622 Mbps. The distributed cell scheduling and cell queueing and dequeueing allows this architecture to be scaled to a large number of inputs and outputs.

Keywords

CMOS logic circuits; VLSI; logic design; queueing theory; scheduling; semiconductor switches; switching networks; 0.18 micron; 622 Mbit/s; CMOS standard-cell technology; VLSI; combined input output queued switches; crossbar switches; dequeueing; design complexity; distributed cell queueing; distributed cell scheduling; enhanced crossbar CIOQ switch architecture; line rate; Bandwidth; CMOS technology; Communication switching; Computer architecture; Fabrics; Scheduling; Switches; Throughput; Traffic control; Very large scale integration;

fLanguage

English

Publisher

ieee

Conference_Titel

Electrical and Computer Engineering, 2004. Canadian Conference on

ISSN

0840-7789

Print_ISBN

0-7803-8253-6

Type

conf

DOI

10.1109/CCECE.2004.1345297

Filename

1345297