Low power strategy about correlator array for CDMA baseband processor

Author

Ku, Chung-Wei ; Kuo, Fu-Yen ; Chen, Chi-Kuang ; Chen, Liang-Gee

Author_Institution

Comput. & Commun. Res. Labs., ITRI, Taiwan

fYear

1999

fDate

6/21/1905 12:00:00 AM

Firstpage

513

Lastpage

522

Abstract

This paper discusses the design, implementation, and performance evaluation of a low powered correlator architecture for multi-code CDMA systems. In CDMA systems, correlators are used to de-spread the received signals and are important blocks for RAKE receivers. We proposed a low powered correlator architecture to de-spread input with several PN sequence concurrently, According to our preliminary simulation results, the suggested architecture can de-spread the input signal with two PN codes simultaneously and save 41% power consumption compared with traditional correlator architecture

Keywords

code division multiple access; correlators; performance evaluation; pseudonoise codes; radio receivers; CDMA baseband processor; PN sequence; RAKE receivers; correlator array; low power strategy; multi-code CDMA systems; performance evaluation; 3G mobile communication; Baseband; Correlators; Data communication; Digital signal processing chips; Energy consumption; Multiaccess communication; Power engineering computing; Working environment noise; Yttrium;

fLanguage

English

Publisher

ieee

Conference_Titel

Signal Processing Systems, 1999. SiPS 99. 1999 IEEE Workshop on

Conference_Location

Taipei

ISSN

1520-6130

Print_ISBN

0-7803-5650-0

Type

conf

DOI

10.1109/SIPS.1999.822357

Filename

822357