An improved path sensitization method in test pattern generation for combinational circuits

Author

Chang, Chuan-Wang ; Lee, Shie-Jue

Author_Institution

Dept. of Electr. Eng., Nat. Sun Yat-Sen Univ., Kaohsiung, Taiwan

fYear

1995

Firstpage

678

Lastpage

685

Abstract

We present a fast sensitized path decision method for test pattern generation of combinational circuits. This method accelerates any path sensitization test pattern generation (ATPG) algorithm, such as D-algorithm, PODEM, FAN, or SOCRATES. The essential idea of our method is to propagate the fault on a stem (fanout node) to all its fanout-branches and to desensitize one or more input lines of a reconvergent gate when the fault effect can not propagate through the gate. In this way, the time for selecting paths to be sensitized can be reduced

Keywords

ULSI; automatic test software; combinational circuits; fault diagnosis; integrated circuit testing; logic testing; multivalued logic circuits; ATPG algorithm; D-algorithm; FAN; PODEM; SOCRATES; combinational circuits; decision tree; fast sensitized path decision method; fault propagation; nine valued model; path sensitization method; reconvergent gate desensitization; test pattern generation; Acceleration; Automatic test pattern generation; Circuit faults; Circuit testing; Combinational circuits; Controllability; Costs; Large-scale systems; Test pattern generators; Ultra large scale integration;

fLanguage

English

Publisher

ieee

Conference_Titel

Industrial Automation and Control: Emerging Technologies, 1995., International IEEE/IAS Conference on

Conference_Location

Taipei

Print_ISBN

0-7803-2645-8

Type

conf

DOI

10.1109/IACET.1995.527641

Filename

527641