Double injection of a divide-by-2 LC frequency divider to enhance locking range

The work proposed a topology to enhance the locking range of the injection locked ÷2 circuit. The topology uses an in-phase injection of two signals to increase locking range and a current re-used architecture to decrease power consumption. To verify the proposed circuit, the chip was fabricated using TSMC 0.18μm CMOS technology. Measurement shows the input frequency sweeps from 24.5 GHz to 29 GHz and the locking range has 4.5 GHz. The circuit dissipates 1.26mW due to the adoption of current re-used architecture. Therefore, the circuit not only has 4.5 GHz locking range but also dissipates 1.26mW.