A multi-level approach to low power MAC design

Author

Shim, Kihak ; Oh, Ik Kyun ; Hong, Sang Min ; Ryu, Beom Seon ; Lee, Kie Young ; Cho, Tae Won

Author_Institution

Dept. of Electron. Eng., Chung-Buk Nat. Univ., Cheongju, South Korea

fYear

1999

fDate

6/21/1905 12:00:00 AM

Firstpage

723

Lastpage

731

Abstract

A low power 8×8+20-bit MAC is designed minimizing the power consumption at each of the design levels. At algorithm level, a new method for MR-XY operation which saves 40% of transistor counts over conventional methods is proposed. A new Booth selector circuit using NMOS PTL (pass-transistor logic) which has excellent power-delay product is also proposed at transistor level. Dynamic CMOS single edge triggered flip-flops are used to reduce the number of transistors for the registers. The proposed MAC is designed with 0.6 um single-poly triple-metal CMOS process. As a result of simulation, operating frequency is over 100 MHz with 3.3 V supply voltage and the average power consumption is 51 mW at 100 MHz

Keywords

CMOS logic circuits; adders; logic circuits; multiplying circuits; signal processing; Booth selector circuit; MR-XY operation; NMOS PTL; low power MAC design; multi-level approach; pass-transistor logic; power-delay product; single-poly triple-metal CMOS process; CMOS logic circuits; CMOS process; Circuit simulation; Energy consumption; Flip-flops; Frequency; Logic circuits; MOS devices; Registers; Voltage;

fLanguage

English

Publisher

ieee

Conference_Titel

Signal Processing Systems, 1999. SiPS 99. 1999 IEEE Workshop on

Conference_Location

Taipei

ISSN

1520-6130

Print_ISBN

0-7803-5650-0

Type

conf

DOI

10.1109/SIPS.1999.822380

Filename

822380