DocumentCode
1607254
Title
Low power JPEG-2000 image compression for industrial embedded applications
Author
Aouadi, I. ; Hammami, O.
Author_Institution
ENSTA, Paris, France
Volume
3
fYear
2004
Firstpage
1585
Abstract
In this paper we described an implementation for a dual JPEG-2000 entropy coder on FPGA and its integration within a JPEG-2000 software encoder on an industrial platform. The use of FPGA as coprocessor on an industrial platform dramatically improves the performance of the JPEG-2000 encoder especially the entropy coding phase. Implementation on a Xilinx XCV405E allows up to 2 parallel coders because of the important use of the BRAMs.
Keywords
data compression; entropy codes; field programmable gate arrays; image coding; FPGA; JPEG-2000; Xilinx XCV405E; coprocessor; entropy coder; entropy coding; image compression; industrial embedded applications; software encoder; Arithmetic; Code standards; Context modeling; Entropy coding; Hardware; IEC standards; ISO standards; Image coding; Propagation losses; Wavelet transforms;
fLanguage
English
Publisher
ieee
Conference_Titel
Industrial Technology, 2004. IEEE ICIT '04. 2004 IEEE International Conference on
Print_ISBN
0-7803-8662-0
Type
conf
DOI
10.1109/ICIT.2004.1490803
Filename
1490803
Link To Document