• DocumentCode
    1607781
  • Title

    Distributed automatic test pattern generation

  • Author

    Chan, Terence

  • Author_Institution
    Vertex Semicond. Corp., San Jose, CA, USA
  • fYear
    1992
  • Firstpage
    385
  • Lastpage
    388
  • Abstract
    An automatic test pattern generation (ATPG) program which can partition the logic and stuck-at faults of any scan-based ASIC into disjoint sets is described. These logic partitions and fault sets are processed concurrently over a computing network. The performance of the ATPG is improved significantly, and it can handle very large ASICs
  • Keywords
    application specific integrated circuits; automatic testing; fault location; integrated circuit testing; integrated logic circuits; logic testing; ATPG program; automatic test pattern generation; digital IC; disjoint sets; distributed ATPG; fault sets; logic faults; logic partitions; scan-based ASIC; stuck-at faults; Application specific integrated circuits; Automatic test pattern generation; CMOS logic circuits; Circuit faults; Circuit testing; Latches; Logic design; Logic gates; Pins; Workstations;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    ASIC Conference and Exhibit, 1992., Proceedings of Fifth Annual IEEE International
  • Conference_Location
    Rochester, NY
  • Print_ISBN
    0-7803-0768-2
  • Type

    conf

  • DOI
    10.1109/ASIC.1992.270263
  • Filename
    270263
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=1607781