Integration of interconnect process highly manufacturable for 65nm CMOS platform technology (CMOS5)

Author

Honda, K. ; Kanda, M. ; Ishizuka, R. ; Moriuchi, Y. ; Matsubara, Y. ; Habu, M. ; Yoshida, T. ; Matsuda, S. ; Kittaka, H. ; Miyajima, H. ; Hachiya, T. ; Kajita, A. ; Usui, T. ; Nagashima, N. ; Kanamura, R. ; Okamoto, Y. ; Yamada, S. ; Noguchi, T.

Author_Institution

Syst. LSI Div., Toshiba Corp., Semicond. Co., Yokohama, Japan

fYear

2004

Firstpage

62

Lastpage

63

Abstract

PAE/SiOC/SiC hybrid dual damascene process with low-k (k=2.5) dielectric layer for 65nm-node was successfully integrated. The EB curing technique of the low-k dielectric was selected to maintain enough adhesion strength. Package feasibility test was performed successfully. To evaluate the impact of the ILD process on the device performance, gate oxide characteristics was carefully studied and no degradation was observed. Functional logic and memory blocks were fabricated using multi level interconnections. High manufacturability of the hybrid DD interconnects process for the 65nm CMOS platform is demonstrated.

Keywords

CMOS integrated circuits; VLSI; digital storage; integrated circuit interconnections; logic circuits; nanotechnology; 65 nm; 65nm CMOS platform technology; EB curing technique; PAE/SiOC/SiC hybrid dual damascene process; SiC-SiO; adhesion strength; interconnect process; Adhesives; CMOS process; CMOS technology; Curing; Dielectrics; Manufacturing processes; Packaging; Performance evaluation; Silicon carbide; Testing;

fLanguage

English

Publisher

ieee

Conference_Titel

VLSI Technology, 2004. Digest of Technical Papers. 2004 Symposium on

Print_ISBN

0-7803-8289-7

Type

conf

DOI

10.1109/VLSIT.2004.1345394

Filename

1345394