An optimised FPGA configuration for signal processing

A field programmable gate array (FPGA) configuration for digital filtering operations is described. The FPGA is configured as a linear systolic array of logical macrocells in which data are broadcast locally and operated on rhythmically. Templates have been created defining macrocells. Each macrocell is made of a fixed number of configurable layer blocks (CLBs) which could be reconfigured to optimize performance. The logical macrocell structure and the connection topology are examined