• DocumentCode
    1610769
  • Title

    5nm-gate nanowire FinFET

  • Author

    Yang, Fu-Liang ; Lee, Di-Hong ; Chen, Ha-Yu ; Chang, Chang-Yun ; Liu, Sheng-Da ; Huang, Cheng-Chuan ; Chung, Tang-Xuan ; Chen, Hung-Wei ; Huang, Chien-Chao ; Liu, Yi-Hsuan ; Wu, Chug-Cheng ; Chen, Chi-Chun ; Chen, Shih-Chang ; Chen, Ying-Tsung ; Chen, Yin

  • Author_Institution
    Taiwan Semicond. Manuf. Co., Hsin-Chu, Taiwan
  • fYear
    2004
  • Firstpage
    196
  • Lastpage
    197
  • Abstract
    A new nanowire FinFET structure is developed for CMOS device scaling into the sub-10 nm regime. Accumulation mode P-FET and inversion mode N-FET with 5 nm and 10 nm physical gate length, respectively, are fabricated. N-FET gate delay (CV/I) of 0.22 ps and P-FET gate delay of 0.48 ps with excellent subthreshold characteristics are achieved, both with very low off leakage cur-rent less than 10 nA/ μm. Nanowire FinFET device operation is also explored using 3-D full quantum mechanical simulation.
  • Keywords
    CMOS integrated circuits; MOSFET; nanotechnology; nanowires; 0.22 ps; 0.48 ps; 10 nm; 5 nm; 5nm-gate nanowire FinFET; CMOS device scaling; accumulation mode; inversion mode; subthreshold characteristics; Chaos; Delay; FETs; FinFETs; Laboratories; Leakage current; Nanoscale devices; Quantum mechanics; Semiconductor device manufacture; Threshold voltage;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    VLSI Technology, 2004. Digest of Technical Papers. 2004 Symposium on
  • Print_ISBN
    0-7803-8289-7
  • Type

    conf

  • DOI
    10.1109/VLSIT.2004.1345476
  • Filename
    1345476
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=1610769