Opportunities and challenges for high-k gate dielectrics

Some key issues related to the development of high-k dielectric technology, including gate stack processing, formation of interfacial layers, EOT (equivalent oxide thickness) control, thermal stability, leakage current, trapping, and mobility degradation are reviewed and discussed. The problems with the conventional mobility extraction methodology for high-k gated MOSFETs is pointed out, and an improved methodology is demonstrated. A novel electrical characterization technique, named the IETS (inelastic electron tunneling spectroscopy), is shown to be capable of revealing a wealth of information of a MOS structure, including phonon modes of both the electrodes and the gate dielectric, impurity bonding structures, and electronic traps.