A pure logic CMOS based low power non-volatile random access memory

Author

Liye Wang ; Shulong Li ; Liyang Pan

Author_Institution

Inst. of Microelectron., Tsinghua Univ., Beijing, China

fYear

2014

fDate

7-10 May 2014

Firstpage

1

Lastpage

2

Abstract

A 1Kbits ultra-low power Non-Volatile Random Access Memory (NVRAM) based on 0.18μm pure CMOS logic process was proposed. This NVRAN features low power supply, low power consumption, high read speed and high reliability during read operation. The two-dimension array architecture and the high voltage solution contribute to the high area efficiency and application flexibility. The simulation result shows that the read speed can be 267Mb/s. The system´s read operation can perform well under the power supply of 0.7V with the read current of 66.4μA and the read power consumption of 906fJ/bit, while the read speed is still 51.3Mb/s, which is fully applicable in embedded or RFID system.

Keywords

CMOS logic circuits; CMOS memory circuits; integrated circuit reliability; low-power electronics; power consumption; random-access storage; NVRAM; RFID system; bit rate 1 kbit/s; bit rate 51.3 Mbit/s; current 66.4 muA; high read speed; high reliability; high voltage solution; low power supply; pure logic CMOS process; read power consumption; size 0.18 mum; two-dimension array architecture; ultra low power nonvolatile random access memory; voltage 0.7 V; Computer architecture; Microprocessors; Nonvolatile memory; Power supplies; Random access memory; Simulation; Transistors; Low Power; Low Voltage; Non-volatile random access memory; RFID; Standard Process;

fLanguage

English

Publisher

ieee

Conference_Titel

Next-Generation Electronics (ISNE), 2014 International Symposium on

Conference_Location

Kwei-Shan

Type

conf

DOI

10.1109/ISNE.2014.6839382

Filename

6839382