From trace graphs to modular delay-insensitive circuits

The problem of synthesizing modular delay-insensitive circuits specified by a class of trace structures is considered. First, the notion of trace graphs is introduced for the purpose of facilitating the description of the relevant trace structures. Then, a theoretical framework within which the verification problem can be precisely formulated is established. It is shown how the dynamic behavior of a modular network may be derived from the specification of its component modules. The objective of this approach is to prove the correctness of the synthesis algorithm rather than verifying particular asynchronous circuits.