• DocumentCode
    1612567
  • Title

    The positive trigger voltage lowering effect for latch-up

  • Author

    Lee, Jian-Hsing ; Weng, Wu-Te ; Shih, Jiaw-Ren ; Yu, Kuo-Fen ; Tong-Chern Ong

  • Author_Institution
    Taiwan Semicond. Manuf. Co., Hsin-Chu, Taiwan
  • fYear
    2004
  • Firstpage
    85
  • Lastpage
    88
  • Abstract
    In this paper, a new latch-up phenomenon, in which the positive trigger voltage Vtrg+ is smaller than the theoretical value, based on the two-step activation diode model, is found and analyzed by TCAD simulation. Based on the simulation result, an analytical model for the positive trigger point is developed and methodologies for evaluating the positive trigger point, varying with the geometry layout of the latch-up test patterns, are proposed. The calculated positive trigger current and trigger voltage fit the measurement results very well, so that the proposed method is efficient for evaluating the positive triggering point.
  • Keywords
    circuit simulation; equivalent circuits; trigger circuits; TCAD simulation; latch-up pattern layout geometry; latch-up phenomenon; lumped-equivalent circuit; positive trigger current; positive trigger point; positive trigger voltage; positive trigger voltage lowering effect; two-step activation diode model; Analytical models; Bipolar transistors; Circuit simulation; Medical simulation; Predictive models; Semiconductor diodes; Substrates; Testing; Variable structure systems; Voltage;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Physical and Failure Analysis of Integrated Circuits, 2004. IPFA 2004. Proceedings of the 11th International Symposium on the
  • Print_ISBN
    0-7803-8454-7
  • Type

    conf

  • DOI
    10.1109/IPFA.2004.1345550
  • Filename
    1345550