Code reorganization for instruction caches

Conventional cache optimizations are usually confined to hardware. However, software optimizations are more flexible and allow faster hardware due to reduced complexity. The authors describe a method of using direct mapped caches more effectively by adapting program behavior. They introduce coarse-grained code reorganization as a software method of improving instruction cache hit rates. Based on trace analysis, cache conflicts are computed taking into account both temporal and spatial program locality. This leads to a precise prediction of cache behavior which is used to reorganize the code in address space. The potential of the solution is demonstrated by applying the code reorganizer to a variety of SPEC benchmarks. Both simulated and measured results are presented for various cache sizes. The results show significant performance gains across the various SPEC programs evaluated.