A 4-transistor static memory cell design with a standard CMOS process

A static four-transistor memory cell design which can be implemented with a standard CMOS process is presented. By combining dynamic read/write memory operations and static data memorization, no refresh is needed for the memory matrix. With a small cell surface and compatibility with the CMOS logic implementing process, it is very adequate to apply this memory cell design to the onchip memory or register file in DSP VLSI design. A 128-b×8-b experimental memory chip is being fabricated in the French MPC CMOS process with a 2-μm design rule, and the memory cell occupies a surface of 690 μm² , which is equivalent to that of a four-transistor dynamic cell