A test methodology for interconnect structures of LUT-based FPGAs

Author

Michinishi, Hiroyuki ; Yokohira, Tokumi ; Okamoto, Takuji ; Inoue, Tomoo ; Fujiwara, Hideo

Author_Institution

Dept. of Inf. Technol., Okayama Univ., Japan

fYear

1996

Firstpage

68

Lastpage

74

Abstract

In this paper we consider testing for programmable interconnect structures of look-up table based FPGAs. The interconnect structure considered in the paper consists of interconnecting wires and programmable points (switches) to join them. As fault models, stuck-at faults of the wires, and extra-device faults and missing-device faults of the programmable points are considered. We heuristically derive test procedures for the faults and then show their validness and complexity

Keywords

SRAM chips; automatic testing; design for testability; fault diagnosis; field programmable gate arrays; integrated circuit interconnections; logic testing; reconfigurable architectures; sequential circuits; table lookup; ATPG; SRAM based architecture; complexities; extra-device faults; fault models; heuristic derivation; interconnecting wires; logic functions; look-up table based FPGA; missing-device fault; programmable interconnect structure; programmable points; sequential loading; stuck-at faults; test methodology; Circuit faults; Circuit testing; Field programmable gate arrays; Integrated circuit interconnections; Logic circuits; Logic testing; Programmable logic arrays; Switches; Table lookup; Wires;

fLanguage

English

Publisher

ieee

Conference_Titel

Test Symposium, 1996., Proceedings of the Fifth Asian

Conference_Location

Hsinchu

ISSN

1085-7735

Print_ISBN

0-8186-7478-4

Type

conf

DOI

10.1109/ATS.1996.555139

Filename

555139