DocumentCode
1614388
Title
Efficient improvement of hot-carrier-induced degradation for sub-0.1 /spl mu/m CMOSFET
Author
Chieh-Ming Lai ; Yean-Kuen Fang ; Wen-Kuan Yeh ; Chia-Che Hu ; Jung-Chun Lin ; Shing-Tai Pan
Author_Institution
Inst. of Microelectron., Nat. Cheng Kung Univ., Taiwan
fYear
2004
Firstpage
275
Lastpage
278
Abstract
The effect of post-thermal annealing (PA) after halo implantation on the reliability of sub-0.1 /spl mu/m CMOSFETs was investigated. We found that the control of annealing time is more efficient than that of annealing temperature with respect to improving the hot-carrier-induced device degradation. The best results of device performance were obtained with post-annealing treatment performed at medium temperatures for a longer time.
Keywords
CMOS integrated circuits; MOSFET; annealing; doping profiles; hot carriers; integrated circuit reliability; ion implantation; semiconductor device reliability; semiconductor device testing; 0.1 micron; CMOSFET; annealing temperature; annealing time control; device degradation; device performance; halo implantation; hot-carrier-induced degradation; post-annealing treatment temperature; post-thermal annealing; reliability;
fLanguage
English
Publisher
ieee
Conference_Titel
Physical and Failure Analysis of Integrated Circuits, 2004. IPFA 2004. Proceedings of the 11th International Symposium on the
Conference_Location
Taiwan
Print_ISBN
0-7803-8454-7
Type
conf
DOI
10.1109/IPFA.2004.1345622
Filename
1345622
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