A 10b 500MHz 55mW CMOS ADC

Recent work on ADCs targeting sampling rates of hundreds of MHz with resolutions in the range of 10 to 11 b has faced speed limitations with a single channel or employed interleaving, but with a relatively high power dissipation or low SNDR. This paper introduces a calibration technique that, together with a high-speed opamp topology, allows a single channel to operate at 500 MHz and digitize a 233 MHz input with an SNDR of 53 dB. This SNDR yields a figure of merit (FOM) of 0.3 pJ/conversion-step, the lowest reported for 10 and 11 b ADCs running at these frequencies.