SCPC1: silicon compiler pyramidal chip for image processing

Author

Albanesi, M. Grazia ; Ferretti, M.

Author_Institution

Dept. Inf. e Sististica, Pavia Univ., Italy

fYear

1989

Firstpage

191

Abstract

A chip for image processing called SCPC1 (silicon compiler pyramidal chip) is presented. It belongs to the image-processing-dedicated ASIC family and can be used to build massively parallel, hierarchical systems to perform image processing at different levels of resolution. The purpose of this project is twofold: testing the facilities offered by the design tool (a silicon compiler) when managing nonconventional, bit-serial architectures and obtaining a modular, extendible chip architecture that allows for increased integration of PEs in a single chip

Keywords

application specific integrated circuits; circuit layout CAD; computerised picture processing; digital signal processing chips; parallel processing; PE integration; Si compiler; bit-serial architectures; design tool facility testing; image-processing-dedicated ASIC family; massively parallel hierarchical systems; modular extendible chip architecture; resolution levels; silicon compiler pyramidal chip; Application specific integrated circuits; Computer architecture; Computer vision; Concurrent computing; Data structures; Image processing; Image resolution; Parallel processing; Pixel; Silicon compiler;

fLanguage

English

Publisher

ieee

Conference_Titel

Circuits and Systems, 1989., IEEE International Symposium on

Conference_Location

Portland, OR

Type

conf

DOI

10.1109/ISCAS.1989.100324

Filename

100324