DocumentCode
1615563
Title
Design and Implementation of an Adaptive Algorithm for Hybrid Automatic Repeat Request
Author
Lopacinski, Lukasz ; Nolte, Joerg ; Buechner, Steffen ; Brzozowski, Marcin ; Kraemer, Rolf
Author_Institution
Brandenburg Univ. of Technol., Cottbus, Germany
fYear
2015
Firstpage
263
Lastpage
266
Abstract
Transmission efficiency is an interesting topic for data link layer developers. The overhead of protocols and coding should be reduced to a minimum. This maximizes a link throughput. This is especially important for high-speed networks, where a small degradation of efficiency will degrade the throughput by several Gbps. We describe a redundancy balancing algorithm for an adaptive hybrid automatic repeat request with Reed-Solomon coding. We introduce a testing environment, most important technical issues, and results generated on a field programmable gate array. The hybrid automatic repeat request and Reed-Solomon algorithms are explained. We provide a mathematical description, and a block diagram of the adaptation algorithm. All necessary algorithm simplifications are explained in details. The algorithm can be represented by basic operations in hardware. In most cases, it finds the optimal coding for a predefined bit error rate.
Keywords
Reed-Solomon codes; automatic repeat request; error statistics; field programmable gate arrays; Reed-Solomon coding; adaptation algorithm; adaptive algorithm design; adaptive algorithm implementation; adaptive hybrid automatic repeat request; bit error rate; block diagram; coding overhead; data link layer; field programmable gate array; high-speed networks; hybrid automatic repeat request; link throughput maximization; optimal coding; protocol overhead; redundancy-balancing algorithm; testing environment; transmission efficiency; Bit error rate; Encoding; Field programmable gate arrays; Forward error correction; Redundancy; Throughput; Wireless communication; 100Gbps; FPGA; data link layer; forward error correction; hybrid ARQ; reed-solomon;
fLanguage
English
Publisher
ieee
Conference_Titel
Design and Diagnostics of Electronic Circuits & Systems (DDECS), 2015 IEEE 18th International Symposium on
Conference_Location
Belgrade
Print_ISBN
978-1-4799-6779-7
Type
conf
DOI
10.1109/DDECS.2015.32
Filename
7195708
Link To Document