Stability/performance assessment of monolithic 3D 6T/8T SRAM cells considering transistor-level interlayer coupling

Author

Ming-Long Fan ; Hu, Vita Pi-Ho ; Yin-Nien Chen ; Pin Su ; Ching-Te Chuang

Author_Institution

Dept. of Electron. Eng., Nat. Chiao Tung Univ., Hsinchu, Taiwan

fYear

2014

fDate

28-30 April 2014

Firstpage

1

Lastpage

2

Abstract

In this work, we investigate the impact of interlayer coupling on monolithic 3D 6T/8T SRAM cells with various layouts and tier combinations. Our results indicate that for 3D 6T SRAM cell with NFET in top layer, aligning upper-tier pull-down NFET with bottom-tier pull-up PFET enables better cell stability. For monolithic 3D 8T cell, an area-efficient 4N4P design is evaluated with optimized two-tier layout to enhance cell performance. We find that stacking NFET layer over the PFET tier results in larger design margins for SRAM cell stability and performance.

Keywords

SRAM chips; circuit stability; field effect transistors; integrated circuit layout; area-efficient 4N4P design; bottom-tier pull-up PFET; for SRAM cell stability; monolithic 3D 6T/8T SRAM cells; optimized two-tier layout; stability-performance assessment; stacking NFET layer; transistor-level interlayer coupling; upper-tier pull-down NFET; Contracts; Couplings; Niobium; SRAM cells; Three-dimensional displays; Wireless sensor networks;

fLanguage

English

Publisher

ieee

Conference_Titel

VLSI Technology, Systems and Application (VLSI-TSA), Proceedings of Technical Program - 2014 International Symposium on

Conference_Location

Hsinchu

Type

conf

DOI

10.1109/VLSI-TSA.2014.6839680

Filename

6839680