DocumentCode
1617337
Title
Linearity improvement base on digital foreground calibration algorithm for a ultra high-speed analog-to-digital converter
Author
Zhang, Ruitao ; Yu, Jinshan ; Zhang, Zhengping ; Wang, Yonglu ; Can, Zhu ; Zhou, Yu
Author_Institution
Nat. Lab. of Analog IC´´s, Chongqing, China
fYear
2010
Firstpage
130
Lastpage
133
Abstract
In this paper, a digital calibration algorithm for an ultra high-speed folding and interpolating analog-to-digital converter in 0.18-μm CMOS technology is presented. The spice simulation result shows the digital foreground calibration algorithm can efficiently improve the linearity of the ADC.
Keywords
CMOS digital integrated circuits; analogue-digital conversion; calibration; CMOS technology; digital foreground calibration algorithm; linearity improvement; size 0.18 mum; ultra high-speed analog-to-digital converter; ultra high-speed folding; Adders; CMOS integrated circuits; Calibration; Clocks; Interpolation; Linearity; Simulation; Ultra High-Speed; analog-to-digital converter; folding; interpolating;
fLanguage
English
Publisher
ieee
Conference_Titel
Anti-Counterfeiting Security and Identification in Communication (ASID), 2010 International Conference on
Conference_Location
Chengdu
Print_ISBN
978-1-4244-6731-0
Type
conf
DOI
10.1109/ICASID.2010.5551519
Filename
5551519
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