DocumentCode
161745
Title
CoWoS™ technologies
Author
Shin-Puu Jeng
Author_Institution
TSMC, Hsinchu, Taiwan
fYear
2014
fDate
28-30 April 2014
Firstpage
1
Lastpage
1
Abstract
Summary form only given. CoWoS™ technology is a full 3D IC integration, which offers unique values of simplified integration, favorable yield, and fast time-to-market. The technology is ideal for thin wafer integration flow, as the thin TSV wafer is always protected. The wafer level integration minimizes warpage, which is critical for μ-bump stacking yield and reliability. The advantages of CoWoS get better for larger size chips. The design reference flow is deployed, and full design methodology and kits are ready. The CoWoS technology passed package and product qual on multiple products, and achieved excellent yield in production.
Keywords
integrated circuit design; integrated circuit reliability; three-dimensional integrated circuits; wafer level packaging; μ-bump stacking yield; CoWoS technology; design reference flow; full 3D IC integration; full design methodology; reliability; size chips; thin TSV wafer; thin wafer integration flow; wafer level integration; Three-dimensional displays; Through-silicon vias;
fLanguage
English
Publisher
ieee
Conference_Titel
VLSI Technology, Systems and Application (VLSI-TSA), Proceedings of Technical Program - 2014 International Symposium on
Conference_Location
Hsinchu
Type
conf
DOI
10.1109/VLSI-TSA.2014.6839701
Filename
6839701
Link To Document