CMOS switched-voltage circuits for signal processing

Author

Handkiewicz, Andrzej

Author_Institution

Inst. of Electr. Eng., Tech. Univ. of Poznan, Poland

fYear

1992

Firstpage

733

Abstract

The possibility of using the switched-voltage (SV) technique for a CMOS standard process is explored. Simple blocks which realize signal inversion, summation and delay, based on voltage inverters, are proposed. SV circuits are modeled using SPICE and compared to their switched-current (SI) counterparts based on current mirrors. These simulations show that the error, caused by the clock feed-through effect is smaller in the SV stage than in the SI one

Keywords

CMOS integrated circuits; SPICE; analogue processing circuits; circuit analysis computing; invertors; switched networks; CMOS switched-voltage circuits; SPICE; SV circuits; clock feed-through effect; delay; signal inversion; summation; voltage inverters; CMOS process; CMOS technology; Delay; Inverters; Mirrors; SPICE; Semiconductor device modeling; Signal processing; Switching circuits; Voltage;

fLanguage

English

Publisher

ieee

Conference_Titel

Circuits and Systems, 1992., Proceedings of the 35th Midwest Symposium on

Conference_Location

Washington, DC

Print_ISBN

0-7803-0510-8

Type

conf

DOI

10.1109/MWSCAS.1992.271219

Filename

271219

Link To Document

https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=1618884