Electromigration-induced failure analysis of VLSI interconnection components

An analysis of electromigration-induced failure effects in various VLSI interconnection components is conducted using the series model of the failure mechanism. The components include a straight segment, a bend, a step, a via, a multisection interconnection and a power/ground bus. By considering the effects of the average flux density and the bamboo phenomenon on the grain boundary migration, each interconnection component is reduced into a series-parallel combination of straight segments. For each of the above-mentioned components, the dependence of the median-time-to-failure and the lognormal standard deviation of the corresponding failure distribution on the various component parameters is investigated. Results can be used for minimizing the interconnection failure due to electromigration