A digitally controlled compact 57-to-66GHz front-end in 45nm digital CMOS

Recently, 60 GHz receiver front-ends have emerged, aiming for very high-data-rate communication. From a cost perspective, a highly integrated solution is favorable. Speed and power consumption considerations for the high-data-rate digital part of the chip make 45 nm CMOS a very realistic candidate technology for such systems. This work presents a 150times50 mum² 60 GHz low 1/f noise direct-downconversion front-end in 45 nm low-power (LP) digital CMOS technology. Its low area, all-digital control (no external bias voltage has been used) and low power consumption make it highly suitable for phased-array systems. Further, a sufficiently large bond pad and optional ESD protection make it practically applicable. Only standard technology features have been used.