A review on low-voltage BiCMOS circuits and a BiCMOS vs. CMOS speed comparison

Proposals on low-voltage BiCMOS basic logic gates are reviewed, and low-voltage BiCMOS speed is compared with CMOS speed. In relation to the BiCMOS vs. CMOS speed comparison, it is shown that the gate delay at fanout of about 5 is a good measure of the relative delay of CMOS/BiCMOS optimized buffers. Analyzing 3.3-V BiCMOS macro as an example, it is shown that the most notable speed merit of 0.5-μm BiCMOS comes from emitter-coupled logic (ECL)-like circuits such as bipolar comparators and bipolar hit logic in cache macros