Evaluation of power gating under transistor aging effect issues in 22nm CMOS technology

Power gating is an effective low-power design technique and is the most widely adopted leakage current reduction solution. In this project, we evaluate the effectiveness of power gating in 22 nm CMOS and analyze the impacts of the Positive/Negative Bias Temperature Instability (PBTI/NBTI) phenomenon on the power gating technique. We also estimate the actual temperatures of power gated circuits and simulate them under different temperatures. The results show that power gating can reduce the effect of PBTI/NBTI, effectively save power, and reduce temperature and delay in hospitable situations while it may not be a good choice in all cases.