Performance estimates of an embedded CPU for high-speed packet processing

Author

Sato, Takao ; Moungnoul, Phichet ; Chivapreecha, Sorawat ; Higuchi, Kenichi

Author_Institution

Comput. & Networking Center, Hirosaki Univ. Hirosaki, Hirosaki, Japan

fYear

2014

fDate

14-17 May 2014

Firstpage

1

Lastpage

5

Abstract

This paper states an embedded CPU performance required for processing packets at a continuous throughput of 1 Gbps. And the out-of-order execution of packets is proposed for processing a variety of packet frame size in the CPU performance. Despite the requirement of high-speed network connections in embedded devices and mobile devices, it is not realized that an embedded CPU capable of high-speed packet processing with low-power operations. In this paper, the authors estimate operating frequencies for processing packets at a continuous throughput of 1 Gbps using a MIPS architecture which is widely used for network devices or embedded systems today. Then, the cases that must be processed with a high-spec CPU is revealed, the solution is proposed. When the frequency of 1.0 GHz and 64-bit registers are used, the CPU usage is 11.0 %.

Keywords

computer architecture; embedded systems; MIPS architecture; bit rate 1 Gbit/s; embedded CPU; frequency 1.0 GHz; high-speed network connection; high-speed packet processing; packet frame size; word length 64 bit; Central Processing Unit; Fires; Firewalls (computing); Multiplexing; Pipelines; Standards; Throughput; 1 Gbps; Embedded CPU; MIPS; multiplexed bus; out-of order; packet processing;

fLanguage

English

Publisher

ieee

Conference_Titel

Electrical Engineering/Electronics, Computer, Telecommunications and Information Technology (ECTI-CON), 2014 11th International Conference on

Conference_Location

Nakhon Ratchasima

Type

conf

DOI

10.1109/ECTICon.2014.6839849

Filename

6839849