Memory performance in chip-on-chip packages: Optimizing memory/ASIC integration

Chip-on-chip MCM packaging combines the benefits of conventional MCM methods with conventional ASIC/commercial memory printed circuit board design methods. COC can reduce board space, increase performance, maintain a cost competitive position and offer an alternative to embedded SRAM and DRAM in the appropriate situations. We show that additional testing for known-good-die is minimal, functional to parametric memory yield is very high, COC module assembly is simple and straightforward, and final packaging is essentially identical to conventional ASIC packaging processes