FPGA implementation of feature extraction algorithm for speaker verification

Speaker identification is a computationally demanding task. Particularly the stage of feature extraction, that is responsible for reducing the resources required to describe speech samples accurately requires algorithms of large complexity. State of the art speaker verification systems are based on cepstral features like MFCC, LFCC or LPCC. In these methods of features extraction the most computing extensive part is spectral averaging using windows in frequency domain. In this paper we propose a feature extraction system based on the LFCC with novel architecture for spectral averaging. Proposed solution is optimized for implementation in programmable structures as System on Programmable Chip and significantly reduces feature extraction execution time.