Effect of load current on fault location estimates of impedance-based methods

Impedance-based methods use simple load models to estimate fault location. However loads in a practical system do not conform to the simplified load models leading to an adverse impact on accuracy of estimation. The objective of this paper is to analyze the effect of load current on fault location estimates of the Takagi, positive-sequence reactance and loop reactance methods. The derivations of the three methods are presented paying special attention to load modeling. The methods are then used to conduct fault location analysis on a modified version of the IEEE 34-Node Test Feeder. The analysis is repeated using the long and lightly loaded original test feeder. When these feeders operate under no-load conditions, fault location estimates of all three methods are highly accurate. Increase in level of load current on both feeder conditions does not affect the accuracy of the Takagi and positive-sequence reactance methods severely. They can be used to locate faults under light-load and heavy-load conditions on short as well as long feeders. The loop reactance method gives highly erroneous estimates when load current magnitude is increased.