DocumentCode
1622725
Title
Systematic architecture design for highly parallel image processing array
Author
Isshiki, Tsuyoshi ; Takeuchi, Yoshinori ; Kunieda, Hiroaki
Author_Institution
Dept. of Electr. & Electron. Eng., Tokyo Inst. of Technol., Japan
fYear
1992
Firstpage
299
Abstract
A methodology for designing the architecture of the processor array for a wide class of image processing algorithms is proposed. A concept of spatially expanding the signal flow graph (SFG) description which enables handling the problem as merely one-dimensional signal processing is used in constructing the methodology. The problem of I/O interface which is critical in real-time processing is also considered
Keywords
image processing; parallel architectures; I/O interface; image processing algorithms; image processing array; one-dimensional signal processing; processor array; real-time processing; signal flow graph; Algorithm design and analysis; Computer architecture; Delay; Design engineering; Design methodology; Image edge detection; Image processing; Pixel; Processor scheduling; Proposals;
fLanguage
English
Publisher
ieee
Conference_Titel
Circuits and Systems, 1992., Proceedings of the 35th Midwest Symposium on
Conference_Location
Washington, DC
Print_ISBN
0-7803-0510-8
Type
conf
DOI
10.1109/MWSCAS.1992.271377
Filename
271377
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