Trade-offs in mapping high-level dataflow graphs onto ASIPs

Data-flow based design environments bring advantages of specification, validation and synthesis to embedded systems design by decoupling computation from transfer of data. The former is performed by actors, and data transfer between actors and an execution order of actors is determined by scheduling and buffering strategies. In this work, we examine code sizes and cycle counts resulting from combinations of scheduling and buffering techniques. The experiments were carried out by designing an application specific instruction-set processor streamlined for each of the benchmarks, using a codesign environment called TCE. We also show what additional overhead is introduced when an architecture implemented using our approach is employed for an application outside its targeted domain.