Comparison of fast modular multiplication architectures in FPGA

Author

Rahman, Mostafizur

Author_Institution

Dept. of Electr. & Comput. Eng., Univ. of Massachusetts Amherst, Amherst, MA, USA

fYear

2010

Firstpage

45

Lastpage

48

Abstract

Modular multiplication is the fundamental operation in most public-key cryptosystem. Therefore, the efficiency of modular multiplication directly affects the efficiency of whole crypto-system. This paper presents implementation and comparison of several recently proposed, highly efficient architectures for modular multiplication on FPGAs: interleaved multiplication, two variants of Montgomery multiplication, Jeong-Burleson multiplication, multiplication based on key size partitioning and complement. Finally, new hardware architecture for time optimal modular multiplication is proposed based on Hamming weight and position of one´s in multiplicand.

Keywords

field programmable gate arrays; public key cryptography; FPGA; Hamming weight; Jeong-Burleson multiplication; Montgomery multiplication; hardware architecture; interleaved multiplication; key size partitioning; modular multiplication architectures; public-key cryptosystem; time optimal modular multiplication; Algorithm design and analysis; Field programmable gate arrays; Hardware; Partitioning algorithms; Random access memory; Table lookup; Cryptography; FPGA; Hardware Implementation; Modular multiplication;

fLanguage

English

Publisher

ieee

Conference_Titel

Anti-Counterfeiting Security and Identification in Communication (ASID), 2010 International Conference on

Conference_Location

Chengdu

Print_ISBN

978-1-4244-6731-0

Type

conf

DOI

10.1109/ICASID.2010.5551841

Filename

5551841