Panel: Software practices for verification/testbench management

The ever rising complexity of current hardware designs and the huge cost penalty of delivering a faulty product have led to a growing investment in functional verification and in the development of new technologies and methodologies in this area. The traditional HDL based testbenches are not proving sufficient for verification. Verification teams are switching to languages such as C++, SystemC or HVLs (High Level Verification Languages) such as Vera, e, SystemVerilog where they can manage the complexity in a more efficient manner. They are adopting concepts such as Object and Aspect Oriented Programming to impart structure to their respective verification infrastructures. In fact building a well equipped testbench for an industrial scale design is equivalent to developing quite complex software. However, such an extensive borrowing from software arena heralds the spillover of problems associated with traditional complex software development. The issues at hand are further aggravated with hardware domain specific issues such as concurrency, timing etc.