Implications of record peak current density In0.53Ga0.47As Esaki tunnel diode on Tunnel FET logic applications

Inter-band tunnel field effect transistors (TFETs) have recently gained a lot of interest because of their ability to eliminate the 60mV/dec sub-threshold slope (STS) limitation in MOSFET. This can result in higher I_on-I_off ratio over a reduced gate voltage range, thus predicting TFETs superior for low supply voltage (VDD ≤ 0.5V) operation. Unlike Si and Ge, III-V semiconductors like In_0.53Ga_0.47As have smaller tunneling barrier and tunnelling mass, thus making them a design choice to eliminate drive current (I_οn) limitations in TFETs. In this work, (i) we present the experimental demonstration of record peak current density (Jpeak) In_0.53Ga_0.47As Esaki tunnel diode, formed using MBE grown in-situ doped epitaxial layers, (ii) Using a non-local tunneling model in Sentaurus device simulator, the measured current-voltage characteristics (J-V) is modeled and the model parameters are calibrated, (iii) Novel In_0.53Ga_0.47As ultra thin body (7nm)-double gate-TFET (UTB-DG-TFET) design to boost I_οn is discussed using the calibrated non-local tunneling model, (iv) Pulse transient response of the novel In_0.53Ga_0.47As TFET inverter is presented and compared with Si based MOSFET inverters at a supply voltage of 0.5 V.